This invention relates in general to techniques for testing integrated circuit chips ("ICs") having an electrically programmable read-only-memory ("ROM") embedded within logic or other digital circuitry on the chip and in particular, to a technique and apparatus for programming and testing at least a portion of the embedded electrically programmable ROM concurrently with and using the same IC tester for functionally testing the logic or other digital circuitry on the chip.
If an electrically programmable ROM is embedded among logic or other digital circuitry on an IC, it is preferable for an IC tester which is functionally testing the logic and other digital circuitry on the IC, to also test at the same time at least a portion of the electrically programmable ROM. For one reason, access to the embedded ROM by sources external to the IC may be limited or restricted in some way, thus making testing of the embedded ROM difficult for a standard memory device tester. For example, since the primary purpose of the embedded ROM is generally to provide fixed data to the logic or other digital circuitry on the IC, parallel data access to sources external to the IC is not normally required. Therefore, only serial access might be provided to external sources to reduce pin-count on the packaged IC. In addition, special address coding and data storage schemes might be used to optimize the access and utilization of the embedded ROM by internal logic or digital circuitry on the IC. As a consequence, direct access to the embedded ROM from external sources may not be possible and indirect access may require the processing of external data requests to pass through special decoding logic on the IC.
Another reason why it is advantageous for the IC tester to test the electrically programmable ROM is that it can do this on a bit-by-bit basis. By having the IC tester test the electrically programmable ROM portion of the IC on a bit-by-bit basis by programming and then verifying the programming of each test bit before testing a next test bit in the electrically programmable ROM, testing of the ROM can be stopped immediately upon first detection of a failure. This ensures that additional programming and test time is not wasted on a "bad" part. In contrast, if the electrically programmable ROM is tested by first programming it on a separate programming device and then verifying the programmed device on a standard memory tester or the IC tester, all of the test bits must be programmed before any of the programmed test bits can be verified. This approach results in completely programming all of the test bits of a "bad" part and consequently, wasting programming time on the programming device. As an example, in some electrically programmable ROM technologies this programming time can be significant (e.g., on the order of .apprxeq.25.0 msec. per bit, or .apprxeq.100 seconds to program a 512 byte memory).
Having the IC tester both program and subsequently verify the programming of a test bit in the electrically programmable ROM presents a problem, however, because the typical programming voltage (.apprxeq.12.0 to 18.0 volts) required to program an electrically programmable ROM is significantly higher than the typical HIGH and LOW logic level voltages (.apprxeq.5.0 and 0.0 volts) required for reading the programmed electrically programmable ROM and functionally testing the logic or other digital circuitry on the IC.
If the IC tester has switchable alternate and primary reference voltage supplies ("RVS.sub.s ") available on each of its test channels, then one method of solving the high voltage problem is to set the primary RVS.sub.s on all of the test channels to a value suitable for testing the logic or other digital circuitry on the IC, and set the alternate RVS.sub.s on at least one of the test channels to the higher programming voltage required for programming the electrically programmable ROM. Thereafter, when data is to be read from the electrically programmable ROM or the logic or other digital circuitry on the IC is to be tested, the selected test channel having its alternate RVS.sub.s set to the higher programming voltage can be set to its primary RVS.sub.s, and when the electrically programmable ROM is to be programmed, it can be switched to the alternate RVS.sub.s.
Although this method can be used with a standard IC tester to program a test bit and subsequently verify the programmed test bit, switching between the primary and alternate RVS.sub.s cannot readily be done during functional testing of the IC. Consequently, functional testing must stop each time the reference voltage supply for a test channel is switched from the primary to the alternate RVS.sub.s, and vice versa. When a large number of test bits are being programmed in this way, the turning off and on of functional testing and then, repeatedly switching between the primary and alternate RVS.sub.s can be time consuming and consequently, costly in terms of tester and/or operator time.
In addition to the problem of generating the required high programming voltage on the IC tester, another problem is generating a test program which commands the IC tester to generate the required high programming voltage during functional testing of the logic or other digital circuitry. Typically, the test program is at least partially software generated from data resulting from a computer simulation of the IC. Since generally the simulation program only simulates the functionality of the logic or other digital circuitry on the IC, only HIGH and LOW logic levels ("1's" and "0's") are simulated and consequently, only their corresponding voltage levels (e.g., .apprxeq.5.0 and 0.0 volts) are programmed into the test program.
Therefore, to generate the programming voltage (e.g., .apprxeq.12.0 to 18.0 volts) required to program an electrically programmable ROM embedded within the logic or other digital circuitry on the chip, the test program generated from the simulation data would generally be manually modified by a computer programmer to include additional steps, such as turning functional testing off and on, and switching the reference voltage supply between the primary and alternate RVS.sub.s back and forth on at least one selected test channel. When there are a large number of test bits to be programmed, such manual intervention can be not only time consuming, but also lead to error.